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write through cache and hit ratio

Discussion in 'Engineering Concepts' started by huda, Jan 22, 2009.

  1. huda

    huda New Member

    is there any benefit from hit ratio in write
    through cache case?
  2. xpi0t0s

    xpi0t0s Mentor

  3. huda

    huda New Member

    this one of questions of is mano in his book. I tried to resolve it but im not sure.I sent my inquiry about write through in earlier thread , because I have confused in this part .

    q:the access time of cache memory is 100 ns and that of main memory
    1000 ns. it is estimated that 80% of the memory requests are for read
    and the remaining 20% for write. the hit ratio for read access only is
    0.9. a write -through procedure is used.
    a- what is the average access time of the system considring only
    memory read cycles?
    b-what is the average access time of the system for both read asn
    write requests?
    c-what is the hit ratio taking into consideration the write cycles?

  4. xpi0t0s

    xpi0t0s Mentor

    A write through procedure basically means that the cache and main memory will be written to - this should be explained in the book. What I don't know is if those operations are parallel or sequential - in other words, does a write take 1000ns or 1100ns. This should also be explained in the book.

    So the questions are increasingly complex. The average access time considering read-only cycles - as I said before, I find it easier to use numbers. Let's say there are 100 reads. The hit ratio for read access is 0.9 so 90 reads will be from cache and 10 will be from main memory. The total time for the reads from cache is 90*100ns and the total time for the reads from memory is 10*1000ns. Total is 90*100+10*1000=9000+10000=19000. The average access time is the total access time divided by the number of accesses, which is 19000/100, which is 190ns.

    For b we need to add in the write times which you'll need to find out from the book if they are 1000ns or 1100ns. If 1100ns then for 100 accesses, 80% are read, so that's 80 read and 20 write. Of the 80 read the hit ratio is 0.9 so that means there are 72 (90% of 80) cache reads and 8 reads from main memory. So the total is 1100*20 for the writes + 72*100 for the cache reads + 8*1000 for the cache misses = 1100*20+72*100+8*1000 = 22000+7200+8000 = 37200. There were 100 accesses so the average access time is 37200/100=372, or a slightly lower value which you can calculate for yourself if the write time is 1000.

    Actually I'm not sure about c. The hit ratio for writes is either zero or 100% depending how you look at it. If a hit simply means the write went to cache regardless of whether or not it went to main memory as well, then the ratio is 100%. But if a hit means we bypassed main memory access altogether then the write hit ratio is zero. This should be clarified in the book.

    So for example if the write hit ratio is considered to be zero on the grounds that no write bypasses a main memory access, then for 100 accesses again, 72 will be reads from cache, 8 will be reads from memory and 20 will be writes to memory (and cache). Total cache hits, aka memory misses, is 72 out of 100, which is 72% or a total hit ratio of 0.72.

    Or perhaps the writes are sequential instead of parallel. Then the number of writes is effectively doubled, so in 120 accesses there will be 80 reads (72 cache, 8 memory), 20 writes to cache and 20 writes to memory. Total cache hits is 72+20=92, giving a cache hit ratio of 92/120=76.(6)%.

    Or maybe this should be 80 reads (72 cache, 8 memory), 10 cache writes, 10 memory writes; cache hits are 72+10=82 for a hit ratio of 82%. I think the answer most likely to be correct is the first, i.e. 0.72, where a single write constitutes a write to cache and a write to main memory.
  5. huda

    huda New Member

    yes, this what I did , but , I weren't sure from my trying.
    but, as morris mentioned in his book, in case of miss ,I have some addition to your resolving.
    regarding read :
    (hit read cache)90*100+(miss read cache)10*100+(miss read memory)10*1000=9000+10000=20000
    because, in miss ,cpu should access to cache at first,then it access to memory.
    please, i need your comments in what I added above
    regarding b and c, you thought in same trend which I thought it.
    but some lecturers in same field weren't agreeing with me in this view.
    any way, morris didn't mention if the access time in write case is 1100 or 1000 directly,but , I think it is 1100, since there is write to cache and memory .
    so, I asked in this thread at first.
    what is the benefit from hit ratio in write through?
    but now, I know there is no any importance for hit ratio in write through.
    are you agree with me?
  6. xpi0t0s

    xpi0t0s Mentor

    There's no need to quote my message in full. This is a forum, not a newsgroup where messages can arrive out of order. Please only quote essential parts, not the full post.

    Yes, the CPU will look at the cache first, but if the item it wan't isn't there then that's only a cache miss. Looking in the cache for something that isn't there doesn't count as a cache hit. Determining whether or not something is in cache needs to be done for every memory read so there doesn't seem any point including this in the count.

    I honestly have no idea if write through caching writes to cache and memory simultaneously or sequentially. That will significantly affect the timing so I would have thought this would be an obvious thing to mention. I guess it could be implemented either way; it depends on the design.

    The hit ratio is only relevant where a cache hit means no access to main memory is made. If you have write through caching then every memory write is also a cache write so the hit ratio is zero or 100% depending how you want to look at it, as previously explained.

    Did the lecturers explain why they didn't agree? I think I listed all possibilities.
  7. huda

    huda New Member

    sorry,im new user in this forum, so,i don't know how i must reply
    thank you for all explanations. really, I'm feeling that there are some matters got more clear.
    regarding those lecturers, they were believing that 90% hit ratio is divided between read and write , i.e. it didn't be hit ratio for only read.
    by that, 72 will be hit for read and 18 for write, but this absolutely isn't convincing,because, it is mentioned that hit just for read.

    anyway, I'm too grateful for you.
    but, there is just another thread relate "how calculate the size of cache memory".
    i hope , you can provide me with some information about the size of cache which is be a different, depending on type of cache.
    keep in your mind, I didn't leave a web is relating cache ,I didn't browse it to look for a way to calculate the size.but, unfortunately there is no such topic.
    I have searched since long time but there isn't any information about that
  8. xpi0t0s

    xpi0t0s Mentor

    I don't understand the question in "how calculate the size of cache memory"; that's why I haven't answered it. It makes no sense to me at all. Could you expand (in that thread, not this one) in more detail what problem you're trying to solve? Do you have a PDF version of the book that I could look at? (because I'm not about to buy a copy of it, and it seems the questions relate to the book content)
  9. oxD

    oxD New Member

    Hello huda
    In this question we have to consider an independent memory organization i.e. cpu can access any level memory be it cache or main memory directly. Check for coherence in memory organization

    a) avg time = 0.9*20[Cache hit]+(1-0.9)[Cache miss]*max(100,1000)[as the org. is independent access is done in parallel fashion] = 118ns

    b)avg time = 0.8 [frequency]*118 [avg. time for read] + 0.2[frequency]*1 [Hit ratio of write as it is parallel and direct main memory access is possible]* 1000 = 294.4

    c) No. of instructions = 100
    write instructions = 20
    read instructions = 80
    hit ratio = 0.9*80[No. of Hits for read] + 1*20[No. hits for write]/100

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