paging in operating system

Discussion in 'Operating System' started by abc1, Jul 5, 2012.

  1. abc1

    abc1 Banned

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    what is paging in operating system?

    I know Paging is one of the memory management technique that uses non-contiguous memory allocation.But I don't know the how paging works.I referred books,but the concept is
    not very much clear to me.Even I searched in google.

    Please can anybody clear my doubts.......
     
  2. _eb75_

    _eb75_ New Member

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    Running whatever code the processor generates addresses built up by compiling and linking of a program.
    These addresses are not real free address in the current physical RAM.
    Therefore we must place the actual code to a free physical RAM location first.
    Unfortunately the free address is not the same generated by the code.
    We need translation from virtual to physical. We need information to tell where the real address is.
    This is a page table.

    How to use it? It would be too slow to seek a memory page table for every access.
    Therefore we have inside the processor translation cache (TLB, can be for ex. 96 entries only).
    A TLB entry provides fast translation. It translates immediately, virtual to physical (for a page, a big block, offset comes from the end of the virtual address). So every access for a big block (for ex. 32 kb) is very fast
    when translation is once built up. If we have not a translation already built up inside the processor, we get a TLB-fault.
    TLB fault handler builds up the translation and the instruction is restarted.
    TLB- fault handler uses page tabe information. If the page is already somewhere in the RAM by the table, making a translation is easy. If not, a page table entry must be created an the code read from the disk to a new free location.


    My simplified pseudo code from my previous post material (_EB75_):


    if( the faulting virtual address is ok)
    {
    if{ a page table entry already exists for this page)
    {
    Build up a new TLB-entry; (we have not enough entries for the whole RAM)
    Return to the task from the interruption;
    else {
    Find a new free RAM area;
    Read the page from disc to this area;
    Build up a new page table entry (and mark as present);
    Build up a new virtual to physical TLB- translation cache entry;
    Return to the task from the interruption;
    else ............

    This simplified pseudo code do not handle everything for ex. we have not any free RAM and we must
    ..........



    My earlier post:”A very compact basics tutorial tool to learn kernel - any use?” was intended to ansver this kind of questions by simple code level examples and pseudo codes.
     
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  3. _eb75_

    _eb75_ New Member

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    I answer to myself, because anybody else do not! No, LOL. The post is same as earlier but I fix my miserable code formatting- more easy to read.

    ----------------------

    Running whatever code the processor generates addresses built up by compiling and linking of a program.
    These addresses are not real free address in the current physical RAM.
    Therefore we must place the actual code to a free physical RAM location first.
    Unfortunately the free address is not the same generated by the code.
    We need translation from virtual to physical. We need information to tell where the real address is.
    This is a page table.



    How to use it? It would be too slow to seek a memory page table for every access.
    Therefore we have inside the processor translation cache (TLB, can be for ex. 96 entries only).
    A TLB entry provides fast translation. It translates immediately, virtual to physical (for a page, a big block, offset comes from the end of the virtual address). So every access for a big block (for ex. 32 kb) is very fast
    when translation is once built up. If we have not a translation already built up inside the processor, we get a TLB-fault.
    TLB fault handler builds up the translation and the instruction is restarted.
    TLB- fault handler uses page tabe information. If the page is already somewhere in the RAM by the table, making a translation is easy. If not, a page table entry must be created an the code read from the disk to a new free location.


    My simplified pseudo code from my previous post material (_EB75_):

    Code:
    TLB_fault_handler {
     if( the faulting virtual address is ok)
      {
          if{ a page table entry already exists for this page)
           {
              Build up a new TLB-entry; (we have not enough entries for the whole RAM)
              Return to the task from the interruption;
            }
          else {
                Find a new free RAM area;   
            Read the page from disc to this area;
            Build up a new page table entry (and mark as present);
            Build up a new virtual to physical TLB- translation cache entry;
            Return to the task from the interruption;
      }
      else ............  
    This simplified pseudo code do not handle everything for ex. we have not any free RAM and we must
    ..........



    My earlier post:”A very compact basics tutorial tool to learn kernel - any use?” was intended to answer this kind of questions by simple code level examples and pseudo codes.
     
  4. _eb75_

    _eb75_ New Member

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    Two comments:

    1. Why you give an example of a RISC- type processor page handing even most familiar processors are CISC- type (Intel/AMD)?
    2. The pseudo code is said to be and is simplified, but still it would good to show how it works in normal multitasking environment. A disk a read is slow and we want start another process to run during the disk read.
     
  5. _eb75_

    _eb75_ New Member

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    You are right. There are two main types of the page table usage, depending on the processor in the question.
    Steps done are the same with both. With "CISC-type" processor OS has less to do, HW- creates TLB translation, if a page table is correct (present), else a page fault is generated.

    With the pseudo code the case is the same, steps are roughly the same but divided into two different places (the fault handler and the disk DMA interrupt handler).

    For a RISC -type processor presented earlier we replace in the pseudo code:

    Code:
    Find a new free RAM area;   
    Read the page from the disc to this area;
    by:
    Code:
    Find a new free RAM area; 
    This process is blocked;  
    Schedule DMA-read of the page from the disc to found free area;//Mark the read to be started by a page fault handler.
    Schedule next ready process to run (do the context switch to this process);
    
    And we must have to complete the whole page fault handling in the disk DMA- interrupt handler.
    Roughly replacing:

    Code:
    Build up a new page table entry (and mark as present);
    Build up a new virtual to physical TLB- translation cache entry;
    Return to the task from the interruption;
    by:
    Code:
    if(read started by the page fault handler)
              {
               Build up a new page table entry (and mark as present);
               Build up a new virtual to physical TLB- translation cache entry;
               The process starting DMA is now ready;
               Schedule next ready process to run (do the context switch to this process);
          }
    Now it is little bit less simplified :nonod:
     
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  6. priya456

    priya456 New Member

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    Paging is a memory management technique in which the memory is divided into fixed size pages. Paging is used for faster access to data. When a program needs a page, it is available in the main memory as the OS copies a certain number of pages from your storage device to main memory.
     
  7. KerryLopez

    KerryLopez New Member

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    The most important thing is that you have to know that paging is a virtual memory mapping scheme.
    It is a page table which is a data structure that translates the virtual address of the process into the physical address of the memory.
     

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