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niranjanvg 6Apr2010 18:46

Problem using Make
 
Hi All,

I am using GNU Make and i have a peculiar kind of error, i am not able to understand, Firstly have a look at the make file used by me


CFLAGS=-c -Wall
CC=gcc
.PHONY:clean
OBJ=./obj
SRC=./src
INC=./inc
exec: $(OBJ)/*.o
$(CC) $^ -o $@
%.o: $(SRC)/*.c
$(CC) $(CFLAGS) $^ -I$(INC)
mv *.o $(OBJ)
clean:
rm -f $(OBJ)/*.o exec



as for as my knowledge goes it is correct, and it execute properly, but the problem is when i change some of my code, and rerun make, it throws a error as below,

gcc -c -Wall src/main.c src/read.c -I./inc
mv *.o ./obj
gcc makefile.o -o makefile
gcc: makefile.o: No such file or directory
gcc: no input files
make: *** [makefile] Error
1


I tried a lot of things but not able to understand why it is happening, if i open the make file and save it, then it works properly, or in other words, if make file is the last one to be edited or it is the one having the latest time stamp than any other file then it is ok, or else it gives an error as above, Kindly help me understand where have i gone wrong in writing the make file.

Thanks & Regards,

Niranjan

xpi0t0s 7Apr2010 18:45

Re: Problem using Make
 
What is your makefile called, and what command do you type to invoke the makefile?

Could you post the makefile again, this time using code tags so that the formatting is preserved? Some lines should be indented and this formatting is removed by the site, so code tags are needed.
For some reason it looks like it is trying to compile "makefile.c", and it's just as well it doesn't work because if the make file is called "makefile" then "gcc makefile.o -o makefile" would overwrite the makefile.

For some reason make is taking the date of the makefile itself into consideration, which it shouldn't do, but this depends on the command and the name of the makefile.

niranjanvg 7Apr2010 19:12

Re: Problem using Make
 
ok My Make file is name "makefile" and i use simple "make" command to invoke it, I am following all the indentations for the rules, anyways have look at my file again.

Repost of my Make file is as below

Code:

CFLAGS=-c -Wall -g
CC=gcc
.PHONY:clean
OBJ:=./obj
SRC:=./src
INC:=./inc
exec: $(OBJ)/*.o
    $(CC) $^ -o $@
%.o: $(SRC)/*.c
    $(CC) $(CFLAGS) $^ -I$(INC)
    mv *.o $(OBJ)
clean:
    rm -f $(OBJ)/*.o exec

As your rightly mentioned it is trying to compile makefile.c which should not be done, and i also found out that the problem is arising because of the pattern matching of wildcard characters used, but am unable to correct it.

And the Error generated is as below

Code:


gcc -c -Wall -g src/main.c src/pop.c src/print_machine.c src/push.c src/read.c src/validate_expr.c -I./inc
mv *.o ./obj
gcc  makefile.o  -o makefile
gcc: makefile.o: No such file or directory
gcc: no input files
make: *** [makefile] Error 1

Regards,
Nianjan


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