A write through procedure basically means that the cache and main memory will be written to - this should be explained in the book. What I don't know is if those operations are parallel or sequential - in other words, does a write take 1000ns or 1100ns. This should also be explained in the book.

So the questions are increasingly complex. The average access time considering read-only cycles - as I said before, I find it easier to use numbers. Let's say there are 100 reads. The hit ratio for read access is 0.9 so 90 reads will be from cache and 10 will be from main memory. The total time for the reads from cache is 90*100ns and the total time for the reads from memory is 10*1000ns. Total is 90*100+10*1000=9000+10000=19000. The average access time is the total access time divided by the number of accesses, which is 19000/100, which is 190ns.

For b we need to add in the write times which you'll need to find out from the book if they are 1000ns or 1100ns. If 1100ns then for 100 accesses, 80% are read, so that's 80 read and 20 write. Of the 80 read the hit ratio is 0.9 so that means there are 72 (90% of 80) cache reads and 8 reads from main memory. So the total is 1100*20 for the writes + 72*100 for the cache reads + 8*1000 for the cache misses = 1100*20+72*100+8*1000 = 22000+7200+8000 = 37200. There were 100 accesses so the average access time is 37200/100=372, or a slightly lower value which you can calculate for yourself if the write time is 1000.

Actually I'm not sure about c. The hit ratio for writes is either zero or 100% depending how you look at it. If a hit simply means the write went to cache regardless of whether or not it went to main memory as well, then the ratio is 100%. But if a hit means we bypassed main memory access altogether then the write hit ratio is zero. This should be clarified in the book.

So for example if the write hit ratio is considered to be zero on the grounds that no write bypasses a main memory access, then for 100 accesses again, 72 will be reads from cache, 8 will be reads from memory and 20 will be writes to memory (and cache). Total cache hits, aka memory misses, is 72 out of 100, which is 72% or a total hit ratio of 0.72.

Or perhaps the writes are sequential instead of parallel. Then the number of writes is effectively doubled, so in 120 accesses there will be 80 reads (72 cache, 8 memory), 20 writes to cache and 20 writes to memory. Total cache hits is 72+20=92, giving a cache hit ratio of 92/120=76.(6)%.

Or maybe this should be 80 reads (72 cache, 8 memory), 10 cache writes, 10 memory writes; cache hits are 72+10=82 for a hit ratio of 82%. I think the answer most likely to be correct is the first, i.e. 0.72, where a single write constitutes a write to cache and a write to main memory.