ok My Make file is name "makefile" and i use simple "make" command to invoke it, I am following all the indentations for the rules, anyways have look at my file again.

Repost of my Make file is as below

Code:
CFLAGS=-c -Wall -g
CC=gcc
.PHONY:clean
OBJ:=./obj
SRC:=./src
INC:=./inc
exec: $(OBJ)/*.o
    $(CC) $^ -o $@ 
%.o: $(SRC)/*.c
    $(CC) $(CFLAGS) $^ -I$(INC)
    mv *.o $(OBJ)
clean:
    rm -f $(OBJ)/*.o exec
As your rightly mentioned it is trying to compile makefile.c which should not be done, and i also found out that the problem is arising because of the pattern matching of wildcard characters used, but am unable to correct it.

And the Error generated is as below

Code:
gcc -c -Wall -g src/main.c src/pop.c src/print_machine.c src/push.c src/read.c src/validate_expr.c -I./inc
mv *.o ./obj
gcc   makefile.o   -o makefile
gcc: makefile.o: No such file or directory
gcc: no input files
make: *** [makefile] Error 1
Regards,
Nianjan