You are right. There are two main types of the page table usage, depending on the processor in the question.
Steps done are the same with both. With "CISC-type" processor OS has less to do, HW- creates TLB translation, if a page table is correct (present), else a page fault is generated.

With the pseudo code the case is the same, steps are roughly the same but divided into two different places (the fault handler and the disk DMA interrupt handler).

For a RISC -type processor presented earlier we replace in the pseudo code:

Code:
Find a new free RAM area;   
Read the page from the disc to this area;
by:
Code:
Find a new free RAM area; 
This process is blocked;  
Schedule DMA-read of the page from the disc to found free area;//Mark the read to be started by a page fault handler.
Schedule next ready process to run (do the context switch to this process);
And we must have to complete the whole page fault handling in the disk DMA- interrupt handler.
Roughly replacing:

Code:
Build up a new page table entry (and mark as present);
Build up a new virtual to physical TLB- translation cache entry;
Return to the task from the interruption;
by:
Code:
if(read started by the page fault handler)
          {
           Build up a new page table entry (and mark as present);
           Build up a new virtual to physical TLB- translation cache entry;
           The process starting DMA is now ready;
           Schedule next ready process to run (do the context switch to this process);
      }
Now it is little bit less simplified
shabbir like this