Because your initial assumptions are wrong:
1 byte instruction takes 1 machine cycle and 4 t-states.
2 byte instruction takes 2 machine cycle and 4+3 t-states.
3 byte instruction takes 4 machine cycle and 4+3+3+3 t-states.
This may be the *general* rule but it doesn't apply to all instructions. A quick google found http://www.google.co.uk/url?sa=t&sou...I5LB2jCA_ZLjXQ
haha, nasty URL, and it's a PDF, but it lists ADC M as 1 byte and 2 M-cycles (1/2), CALL 3/5, CC is 3/2 if the transfer is not taken but 3/5 if it is, and so on. So it is clear that not all instructions follow your 1/1; 2/2; 3/4 assumption.
So read the documentation in detail and do not assume any generalisation holds for *all* possibilities; this is rarely the case.